1. Field of the Invention
The present invention relates to a display device, and more particularly to the enhancement of display performance in a display device by using switching elements alternately in suppression of a threshold voltage of switching elements in a gate signal line drive circuit.
2. Description of the Related Art
Conventionally, for example, with respect to a liquid crystal display device, there has been known a shift register circuit provided to a gate signal line drive circuit for scanning gate signal lines. There may be a case where the shift register circuit adopts a method where the shift register circuit is mounted on the same substrate as thin film transistors (hereinafter referred to as TFTs) arranged in pixel regions, that is, a shift register built-in method. JP-A-2007-95190 discloses a shift register circuit of the related art.
In the shift register circuit, during 1 frame period, a HIGH voltage is outputted to a gate signal line as a gate signal Gout only during a gate scanning period in which a gate signal is outputted to the gate signal line (hereinafter referred to as “signal HIGH period”). Further, during a period other than the signal HIGH period (hereinafter referred to as “signal LOW period”), a LOW voltage is outputted to the gate signal line as the gate signal Gout.
FIG. 12 is a schematic view simply showing the constitution of a basic circuit of the shift register circuit of the related art. The basic circuit of the shift register circuit includes a LOW voltage applying switching element SWA which outputs a LOW voltage to the gate signal line in response to the signal LOW period, and a HIGH voltage applying switching element SWG which outputs a HIGH voltage to the gate signal line in response to the signal HIGH period.
A LOW voltage line VGL is connected to an input side of the LOW voltage applying switching element SWA. To enable the stable outputting of the LOW voltage during the signal LOW period as a gate signal Gout, the LOW voltage applying switching element SWA is turned on in response to the signal LOW period. When the switching element SWA is turned on, the LOW voltage which is the voltage of the LOW voltage line VGL is outputted as the gate signal Gout. Further, the LOW voltage applying switching element SWA is turned off in response to the signal HIGH period. A voltage applied to a switch of the LOW voltage applying switching element SWA is set as a voltage at a node N2. During a period in which the LOW voltage applying switching element SWA is turned on, the voltage at the node N2 assumes a HIGH voltage, and the HIGH voltage is applied to the switch of the LOW voltage applying switching element SWA. Further, during a period in which the LOW voltage applying switching element SWA is turned off, the voltage at the node N2 assumes a LOW voltage, and the LOW voltage is applied to the switch of the LOW voltage applying switching element SWA.
A basic clock signal CLK is inputted to an input side of the HIGH voltage applying switching element SWG. To enable the outputting of the HIGH voltage to the corresponding gate signal line during the signal HIGH period, the HIGH voltage applying switching element SWG is turned on in response to the signal HIGH period so that a voltage of the basic clock signal CLK is outputted as the gate signal Gout. Here, the basic clock signal CLK assumes a HIGH voltage during the signal HIGH period. Further, the HIGH voltage applying switching element SWG is turned off in response to the signal LOW period so that the basic clock signal CLK is interrupted or is not outputted. A voltage applied to a switch of the HIGH voltage applying switching element SWG is set as a voltage at a node N1. During a period in which the HIGH voltage applying switching element SWG is turned on, the voltage at the node N1 assumes a HIGH voltage, and the HIGH voltage is applied to the switch of the HIGH voltage applying switching element SWG. Further, during a period in which the HIGH voltage applying switching element SWG is turned off, the voltage at the node N1 assumes a LOW voltage, and the LOW voltage is applied to the switch of the HIGH voltage applying switching element SWG.
To the switch of the HIGH voltage applying switching element SWG, a switching signal supply switching element SWB which supplies a LOW voltage in response to the signal LOW period is connected. A LOW voltage line VGL is connected to an input side of the switching signal supply switching element SWB. The switching signal supply switching element SWB is turned on in response to the signal LOW period so that the voltage at the node N1 assumes a LOW voltage, and the LOW voltage is applied to the switch of the HIGH voltage applying switching element SWG. Further, the switching signal supply switching element SWB is turned off in response to the signal HIGH period. The voltage which is applied to the switch of the switching signal supply switching element SWB is in common with the voltage which is applied to the switch of the LOW voltage applying switching element SWA so that the voltage is the same voltage at the node N2. During a period in which the switching signal supply switching element SWB is turned on, as described above, the voltage at the node N2 assumes a HIGH voltage, and the HIGH voltage is applied to the switch of the switching signal supply switching element SWB.
FIG. 13 is a circuit diagram showing the basic circuit of the shift register circuit of the related art. As shown in FIG. 13, a transistor T6 provided to a LOW voltage applying switching circuit 211 corresponds to the LOW voltage applying switching element SWA. In the same manner, a transistor T5 provided to a HIGH voltage applying switching circuit 212 corresponds to the HIGH voltage applying switching element SWG. Further, a transistor T2 provided to a switching signal supply switching circuit 213 corresponds to the switching signal supply switching element SWB.
In response to the signal LOW period, the voltage at the node N2 is held at a HIGH voltage, the transistor T6 is turned on, and a low voltage of the LOW voltage line VGL is outputted from an output terminal OUT as the gate signal Gn. Further, the transistor T2 is also turned on so that the voltage at the node N1 is held at the LOW voltage of the LOW voltage line VGL.
On the other hand, although the gate signal Gn−1 of the preceding-stage basic circuit is inputted to an input terminal IN3, a transistor T1 is turned on in response to the signal HIGH period based on the gate signal Gn−1, the voltage at the node N1 assumes the HIGH voltage, and the voltage of the basic clock signal Vn which is inputted from an input terminal IN1 is outputted from the output terminal OUT as the gate signal Gn. Simultaneously, a transistor T7 is turned on based on the gate signal Gn−1 so that the voltage at the node N2 is changed to a LOW voltage. Thereafter, along with a change of the voltage at the node N1 to the HIGH voltage, a transistor T4 is turned on so that the voltage at the node N2 is held at the low voltage of the LOW voltage line VGL.
That is, the voltage at the node N1 is held at the LOW voltage and the voltage at the node N2 is held at the HIGH voltage in response to the signal LOW period, and the voltage at the node N1 is changed to the HIGH voltage and the voltage at the node N2 is changed to the LOW voltage in response to the signal HIGH period.